| Micro hub ASIC |
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| Brief |
| Physical synthesis along with
Floor-planning, Clocktree Generation, 1GHz timing
closure , Place and Route and Physical Verification
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| Design complexity |
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3
clock domain |
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1GHz
Max frequency |
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25
sq. mm Die size |
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TSMC
0.18 micron |
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| Result |
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Ensured a max of only three levels of logic
between flop to flop on 1GHZ paths |
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Timing
Closure complexity met by using a combination
of Physical optimization and clustering of
critical cells by SE-PKS |
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Power
Routing complexity due to irregular shape
of Custom Block & Hierarchy |
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Process,
tools and design stretched to the limits |
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