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The scope of the design included chip level synthesis,
scan/test structure insertion, equivalence checking
and physical synthesis along with floor-planning,
clocktree generation, timing analysis, place and
route and physical verification.
Project highlights were:
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Low power System-on-Chip
design |
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Integrated single-pass
physical design
flow |
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Physical synthesis versus
wireload-based synthesis, thus ensuring better
timing correlation between pre-layout and
post-layout design |
|
Design For Test executed
in the physical design stage |
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