| Device size |
EPLD’s through XCV6000(6 million
gates) |
| Device vendor |
Experience with Xilinx, Altera, Actel,
Lattice |
| Device operating frequency |
200Mhz system performance on a Virtex
FPGA |
| Device usage |
Designs with 100% I/O, and 98% area
used |
| Design complexity |
160Mhz DDR, with 95% device usage
(XCV4000) |
| Domains covered |
Datacom, telecom, multimedia, wireless,
more.. |
| Re-usable design blocks |
Large library of in-house developed
cores, BFM,BM |
| HDL |
Verilog and VHDL expertise |
| Compilation and simulation tools |
Modelsim, NCVHDL, VerilogXL, NCVerilog,
VCS |
| Linting tools |
Explore RTL, LEDA, Wipro SCOUR |
| Synthesis/Physical synthesis |
FPGA compiler, design compiler, synplify,
amplify |
| Place and route |
MaxPlus2, Quartus, Xilinx ISE, Lattice
ISP |