| At Wipro's ASIC design center,
we have the capability to execute projects that
encompass architecture and design to implementation,
synthesis, physical design and silicon validation.
Our extensive portfolio of design wins includes
ASIC designs in 0.13u or tighter geometry, design
sizes in multi-million gates and pin-counts in
excess of 1200 pins. We are a "pure-play
design house" and have targeted designs to
a range of process technologies and libraries.
Likewise, our tools expertise spans the tool families
of Cadence, Mentor, Synopsys and others.
Our design capability includes:
 |
Architecture
definition |
|
Methodology
and tools setup |
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Verification
plan development and verification environment
setup |
|
RTL coding
in Verilog/ VHDL |
|
Deterministic,
random and regression tests |
|
Scan insertion
and design for testability |
|
Synthesis and
netlist generation |
|
Gate level
simulation |
|
Floor planning
and optimization |
|
Place and route
|
|
Static timing
analysis and timing extraction |
|
ATPG/ test
vector generation |
|
Formal verification |
|
