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Case Study

Product Reengineering of a DSP Core

The client

A world leader in digital signal processor (DSP) market and a major player in analog and mixed signal designs.

The challenge

The client required a synthesizable soft macro to be developed for one of their legacy hard macro DSP core. It also involved some design changes to make the new core compatible to latest synthesis libraries.

The solution

Wipro’s engineers converted the legacy design to VHDL RTL conforming functional equivalence as well as keeping the legacy scan chains intact.

Wipro’s contribution can be summed in following activities:

	Converting the legacy design to VHDL RTL
	Checking for formal equivalence between converted RTL and golden netlist
	Converting the old simulation environment to suit new RTL
	Testing new RTL against the simulation environment successfully
	Converting latch based dual clock design to flop based single clock design
	Removing internal tri-states in the design
	Changing the simulation environment to reflect design changes
	Testing changed RTL with changed simulation environment successfully
	Synthesizing the RTL with the latest supplied client library

Key highlights of the project

	Precise documentation defining the scope and the procedure of the exact execution made it easy to track and communicate with non-English customer
	Completely outsourced activity during conversion phase and later in synthesis phase – couple of Wipro team members went to the client’s site to ensure smooth interaction with client’s physical design team.

The benefit

The client could use Wipro’s exposure in executing this type of conversion projects and could get around with the shortage of their engineering resources. Wipro scoped out the complete task, executed it from its own facilities and gave support during physical design while delivering the RTL and set-up and scripts for synthesis, STA and DFT. In addition, Wipro did all the simulation environment changes, which were to be originally done by the client thus leaving the client only the verification responsibility of the same.


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