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Based on the functionality of the block, various
approaches for Block level verification were adopted,
using a combination of behavioral models and random
test benches. Complex DSP blocks were modeled
in SPW (Signal Processing Workstation, from Cadence)
tool. All the block level test benches were designed
to be fully regressionable.
System level verification required the development
of totally 9 system level test benches to test
various sub-functions of the chip.
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The system level test benches were developed
using the FLI (Foreign Language Interface)
interface that enabled coding of the test
cases in C++. The testcases were developed
like C++ device drivers and these were reused
for the ASIC emulation.
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Test benches were developed with dual back-to-back
ASICs to check the base station and remote
terminal interoperation.
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All test benches were fully regressionable.
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The Wipro team also built an emulation board to
verify the functionality of the entire ASIC at a
reduced frequency on Xilinx Vertex FPGAs.
The benefit was the technical acumen displayed
by the Wipro team in the on-schedule and on-budget
verification of a complex 2 mn gate count chip
operating at frequencies in excess of 250 MHz.
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