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Re-engineering was necessary, to increase the
life of the board. Obsolete components were identified,
and appropriate replacement alternatives were
evaluated. Wipro's hardware team took this re-engineering
exercise as an opportunity to explore into a possibility
of cost reduction. Components with cheaper and
more efficient performance characteristics were
carefully chosen to ensure that the stringent
performance parameters were met. Many discrete
components were combined into a single FPGA, older
DRAMs were replaced by faster SDRAMs and old PLDs
/ FPGA devices were replaced with the latest PLDs/FPGA
available from the vendor. Using Verilog-XL, both
as a development and simulation tool, and Cadence
Concept for schematics, a team of five Wipro engineers
delivered the re-designed board in a span of 8
months.
Re-engineering the board resulted in an increase
of its life by a span of 5 years. The customer
was delighted with the dramatic 300US$ decrease
in cost of the board.
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