The project was
carried out in 2 phases.
During Phase 1, Wipro was involved in:
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Test Suite
for Functional co-verification of DiVA blocks.
It covers the tests to verify the design of
20 different blocks within DiVA. |
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A set of Hardware Access
Layer functions to be used by Test Suite.
Later this set also serves as API for the
DiVA. |
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Test segments for Traffic
Tests and Interface Tests in VDLT board, included
the test functions to check the functionalities
of the board. |
|
HAL support for VDLT board,
included the set of library functions for
accessing various devices on the board e.g.
SPI, ATM Processor etc. |
|
Control-E Driver for VDLT
board. A protocol used for communication between
the on board processor and DiVA. |
The Test suite was developed to verify the design
of 20 different clocks within the ASIC. It includes
the Functional testing and Performance Testing.
During Phase-2 of the project Wipro developed test
suite for Performance Testing. Performance Test
suite involved integrating functionalities of all
the DiVA blocks and verifying the capability of
the DiVA against the design specification.
This Phase involved:
|
Test Suite
for Performance verification of DiVA blocks.
It covered the tests to verify the performance
of DiVA when the high traffic is passed. |
|
A set of Hardware Access
Layer functions to be used by Test Suite.
Later this set also serves as API for the
DiVA. |
The test suites and drivers developed during
the project were used to co-verify the ASIC.
Measurable Results
Wipro provided the feedback on design defects
to ASIC design team during Module Testing. This
helped in achieving the first sample rollout of
ASIC with Zero Defect.
Other Business/Technical
Benefits
The successful rollout of the DiVA in 1st sample
itself helped customer in meeting the business
milestone of introducing the next generation DSLAM.
This created a reputation of Wipro in this relatively
new domain.
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